Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology

ABSTRACT

A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent resulted from a continuation application of U.S. patentapplication Ser. No. 09/605,293, filed Jun. 28, 2000, entitled“Semiconductor Devices Including a Layer of Polycrystalline SiliconHaving a Smooth Morphology”, naming David L. Chapek as inventor, whichis a division of U.S. Ser. No. 09/072,262, filed May 4, 1998, now U.S.Pat. No. 6,143,631, the disclosures of which are incorporated herein byreference.

The present invention relates to a method for pretreating a silicondioxide film to provide a polycrystalline silicon film, which issubsequently deposited on the silicon dioxide film, with a smoothmorphology.

BACKGROUND OF THE INVENTION

Advancements in semiconductor manufacture have led to increases in thedensity and miniaturization of microelectronic circuits. As an example,the manufacture of 64 Mb DRAMs is now possible and 256 Mb prototypes arecurrently being developed. A key requirement for achieving such highdevice packing density is the formation of increasingly smallercomponents. One way to make such smaller components is to employ thinnerand smoother films when fabricating those components.

Currently in the art, silicon dioxide films are pretreated with hydrogenions to prepare the surface of the silicon dioxide film for thedeposition of a layer of polycrystalline silicon to provide for athinner and smoother polycrystalline silicon film. The silicon dioxideis pretreated by ion beam bombardment by a Kaufman ion source. Hydrogenion beam pretreatment is typically performed using a Kaufman ion beamsource directed normally to the substrate. A Kaufman ion source employsa metal grid to accelerate ions at a particular target. During an ionimplantation process using a Kaufman ion source, metal from the metalgrid sputters off of the grid and becomes implanted in the target objectcausing the target object to become contaminated. As the size of deviceson the target object decreases, the effect of damage caused by sputteredmetal from the metal grid increases.

Plasma source ion implantation (PSII) has been used to dope variousmaterials, such as tools, aluminum cans and artificial joints, toimprove their wear, friction and corrosion properties. PSII is a processby which ions are implanted into a target at energies high enough tobury the ions below the target's surface. To implant the ions in thetarget, an ionized plasma is formed about the target in an enclosedchamber. A high voltage pulse is applied to the target relative to theconductive walls of the chamber. Ions from the plasma are then driveninto the surfaces of the target from all sides simultaneously withoutany manipulation of the target.

U.S. Pat. No. 4,764,394 to Conrad teaches one method and apparatus forPSII. Conrad describes that plasma source ion implantations may beperformed on complex three-dimensional objects formed from materialssuch as pure metals, alloys, semi-conductors, ceramics and organicpolymers. Conrad describes the process as providing significantincreases in surface hardness of metals and ceramics and providingchanges in the optical properties and electrical conductivity of organicpolymers.

U.S. Pat. No. 5,354,381 to Sheng teaches a plasma immersion ionimplantation apparatus which generally is a variation of the apparatustaught by Conrad. The Sheng apparatus uses a pair of power supplies andvery short ionization negative pulses applied to the cathode underlyingthe target in conjunction with or followed by short ionization pulsesapplied to a second cathode which is facing toward the primary (target)electrode to provide neutralizing electrons.

Thus, a need has developed in the art for a process by which silicondioxide films can be pretreated to ensure that a subsequently depositedpolycrystalline silicon film will be provided with a smooth morphologybut without the contamination problems of present processes.

SUMMARY OF THE INVENTION

The present invention solves that current need by providing a method bywhich a silicon dioxide film is prepared so that a subsequentlydeposited polycrystalline film is deposited smoothly and uniformly ontothe silicon dioxide film.

One aspect of the present invention is directed to a method forcontrolling the morphology of deposited silicon on a layer of silicondioxide. The method comprises the steps of: providing a layer of silicondioxide; implanting hydrogen ions into the layer of silicon dioxide byplasma source ion implantation; and forming a layer of polycrystallinesilicon on the layer of silicon dioxide.

Another aspect of the present invention is directed to a method forpretreating silicon dioxide comprising the steps of: providing a layerof silicon dioxide; and implanting hydrogen ions into a surface of thelayer of silicon dioxide by plasma source ion implantation.

Yet another aspect of the present invention is directed to a method forforming a semiconductor device precursor comprising the steps of:providing a semiconductor substrate; forming a layer of silicon dioxideon the semiconductor substrate; implanting hydrogen ions by plasmasource ion implantation into the layer of silicon dioxide; and forming alayer of polycrystalline silicon on the layer of silicon dioxide.

Still another aspect of the present invention is directed to a methodfor forming a semiconductor device precursor comprising the steps of:providing a semiconductor substrate; forming a layer of silicon dioxideon said semiconductor substrate; exposing said semiconductor substrateto a hydrogen plasma containing hydrogen ions; and applying a highvoltage pulse to said semiconductor substrate thereby implantinghydrogen ions from said ionized hydrogen plasma into a surface of saidlayer of silicon dioxide so that a subsequently formed layer ofpolycrystalline silicon has a smooth morphology.

An additional aspect of the present invention is directed to a methodfor forming a semiconductor device precursor comprising the steps of:providing a semiconductor substrate; forming a layer of silicon dioxideon said semiconductor substrate; exposing said semiconductor substrateto a hydrogen plasma containing hydrogen ions; applying a high voltagepulse to said semiconductor substrate to implant hydrogen ions from saidionized hydrogen plasma into a surface of said layer of silicon dioxideso that a subsequently formed layer of polycrystalline silicon has asmooth morphology; and forming a layer of polycrystalline silicon onsaid surface of said layer of silicon dioxide.

A further aspect of the present invention is directed to a method forforming a semiconductor device comprising the steps of: providing asemiconductor substrate; forming a layer of silicon dioxide on thesemiconductor substrate; implanting hydrogen ions by plasma source ionimplantation into the layer of silicon dioxide; and forming a layer ofpolycrystalline silicon on the layer of silicon dioxide.

Another aspect of the present invention is directed to a method forforming a field effect transistor comprising the steps of: providing asemiconductor substrate having a layer of silicon dioxide formedthereon; implanting hydrogen ions by plasma source ion implantation intothe layer of silicon dioxide; forming a layer of polycrystalline siliconon the layer of silicon dioxide; and forming a source, a drain and agate in the semiconductor substrate to form a field effect transistor.

Still another aspect of the present invention is directed to a methodfor forming a memory array. The memory array includes a plurality ofmemory cells arranged in rows and columns with each of the plurality ofmemory cells including at least one field effect transistor. This methodcomprises the steps of: providing a semiconductor substrate; forming alayer of silicon dioxide on at least a portion of the semiconductorsubstrate; implanting hydrogen ions into at least a portion of the layerof silicon dioxide by plasma source ion implantation; forming a layer ofpolycrystalline silicon over at least the portion of the layer ofsilicon dioxide into which the hydrogen ions were implanted; and forminga gate, a source and a drain for each of the field effect transistors,on the semiconductor substrate.

Yet another aspect of the present invention is directed to asemiconductor device precursor. The semiconductor device precursorincludes a semiconductor substrate. A layer of silicon dioxide is formedon the semiconductor substrate. The layer of silicon dioxide has beendoped with hydrogen ions deposited by a plasma source ion implantationprocess to provide a subsequently deposited layer of polycrystallinesilicon with a smooth morphology. Finally, a layer of polycrystallinesilicon is formed on the layer of silicon dioxide.

An additional aspect of the present invention is directed to a fieldeffect transistor. The field effect transistor includes a semiconductorsubstrate. A layer of silicon dioxide is formed on at least a portion ofthe semiconductor substrate. The layer of silicon dioxide has hydrogenions implanted therein by plasma source ion implantation. A layer ofpolycrystalline silicon is formed on at least a portion of the layer ofsilicon dioxide. A source, a drain and a gate are also formed in thesemiconductor substrate to complete the field effect transistor.

Still yet another aspect of the present invention is directed to amemory array. The memory array comprises a semiconductor substrate. Alayer of silicon dioxide is formed on at least a portion of thesemiconductor substrate. The layer of silicon dioxide has hydrogen ionsimplanted into at least a portion of the layer of silicon dioxide byplasma source ion implantation. A layer of polycrystalline silicon isformed over at least the portion of the layer of silicon dioxide intowhich the hydrogen ions were implanted. A plurality of memory cells arearranged in rows and columns on the semiconductor substrate. Each of theplurality of memory cells comprises at least one field effecttransistor. Gates, sources and drains for each of the field effecttransistors are also formed on the semiconductor substrate.

A still further aspect of the present invention is directed to asemiconductor wafer. The wafer comprises a wafer including asemiconductor substrate. The wafer is divided into a plurality of die. Alayer of silicon dioxide is formed on at least a portion of thesemiconductor substrate. On each of the plurality of die the layer ofsilicon dioxide has hydrogen ions implanted into at least a portion ofthe layer of silicon dioxide by plasma source ion implantation. A layerof polycrystalline silicon is formed over at least the portion of thelayer of silicon dioxide into which the hydrogen ions are implanted. Thewafer also includes a repeating series of gates, sources and drains forat least one field effect transistor formed on each of the plurality ofdie. The series of gates, sources and drains are formed on thesemiconductor substrate.

Another aspect of the present invention is directed to a method formaking a thin film transistor. The method comprises the steps of:providing a semiconductor substrate formed from a material selected fromthe group consisting of silicon dioxide, quartz and glass; forming alayer of a gate oxide material in the semiconductor substrate;implanting, by plasma source ion implantation, hydrogen ions into asurface of the semiconductor substrate; forming a layer ofpolycrystalline silicon on the surface of the semiconductor substrate;forming a layer of an insulating material on the layer ofpolycrystalline silicon; and forming a source region, a drain region anda gate electrode.

Still another aspect of the present invention is directed to a thin filmtransistor. The thin film transistor includes a semiconductor substrateformed from a material selected from the group consisting of silicondioxide, quartz and glass. The semiconductor substrate has hydrogen ionsimplanted therein by plasma source ion implantation. A layer ofpolycrystalline silicon is formed on at least a portion of semiconductorsubstrate. A layer of a insulating material is formed on at least aportion of the layer of polycrystalline silicon. A source region and adrain region are formed on the layer of polycrystalline silicon.Finally, a gate electrode is formed on the layer of insulating material.

It is an object of the present invention to provide a method by which alayer of silicon dioxide, which serves as either a semiconductorsubstrate or another layer on the substrate, can be pretreated so that asubsequently deposited film of polycrystalline silicon can be depositedon the layer of silicon dioxide free of contaminants and have a smoothmorphology. It is also object of the present invention to providevarious semiconductor parts and devices which include a layer ofpolycrystalline silicon having a smooth morphology.

Other objects and advantages of the invention will be apparent from thefollowing detailed description, the accompanying drawings and theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 presents a cross sectional view of semiconductor device precursorformed by the method of the present invention;

FIG. 2 presents a cross sectional view of a field effect transistorformed by the method of the present invention;

FIGS. 2A-2C present cross sectional views of various stages in themanufacture of the field effect transistor shown in FIG. 2;

FIG. 3 shows a schematic view of a memory array formed by the method ofthe present invention;

FIG. 3A shows a schematic view of a memory cell of the memory arrayshown in FIG. 3;

FIG. 4 shows a schematic view of a wafer manufactured by the method ofthe present invention; and

FIG. 5 presents a cross sectional view of a thin film transistor formedby the method of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device precursor 10 formed by the method of the presentinvention is shown in FIG. 1. The precursor 10 includes a semiconductorsubstrate 12, a layer 14 of silicon dioxide 16 and a layer 18 ofpolycrystalline silicon 20. The substrate 12 can be formed of anymaterial currently in use in the art to form substrates forsemiconductors and integrated circuits. For example, the substrate 12can be formed from silicon which can be oxidized to form the layer 14 ofsilicon dioxide 16. Other useful materials for substrate 12 include, butare not limited to, gallium arsenide, indium phosphide, polycrystallinesilicon, silicon dioxide, glass and quartz. Glass, quartz and silicondioxide are particularly useful if the precursor 10 is further processedinto a thin film transistor, such as that described below in connectionwith FIG. 5.

With continued reference to FIG. 1, the layer 14 of silicon dioxide 16is formed on the substrate 12 by any conventional oxidation process ordeposition process, and has been doped with hydrogen ions to provide asurface conducive to the deposition of polycrystalline silicon.Depending upon the nature of the layer 14 of silicon dioxide 16, thelayer 14 of silicon dioxide 16 can be formed by thermal oxidation,chemical vapor deposition (CVD), low pressure chemical vapor deposition(LPCVD), plasma enhanced chemical vapor deposition (PECVD), metalorganicchemical vapor deposition (MOCVD), and sputtering. The layer 18 ofpolycrystalline silicon 20 is formed on the layer 14 of silicon dioxide16 by any deposition process currently used in the art to form a layerof polycrystalline silicon on a layer of silicon dioxide. Usefuldeposition methods include, but are not limited to, CVD, LPCVD, PECVD,MOCVD and sputtering.

The layer 14 of silicon dioxide 16 is doped by plasma source ionimplantation (PSII). Plasma source ion implantation is also referred toas plasma doping (PLAD), plasma immersion ion implantation (PI.sup.3)and plasma implantation (PI). As used herein, the term “plasma sourceion implantation” incorporates and encompasses “plasma doping,” “plasmaimplantation,” and “plasma immersion ion implantation.” A useful plasmasource ion implantation technique and device are taught in U.S. Pat. No.4,764,394 to Conrad, which is incorporated herein by reference in itsentirety. Using the Conrad technique, the substrate 12 is placed in achamber which has walls formed from an electrically conductive material.The substrate 12 is placed on an arm which is electrically connected toa high voltage pulse power supply, such as a pulse line-pulsetransformer type or a high voltage tube modulated pulser. The chamber isfilled with hydrogen gas under a very low pressure in the range of formabout 10.sup.−1 to about 10.sup.−4 Torr. The gas is; then ionized toform a plasma containing hydrogen ions. The plasma can be generated byany of a variety of plasma sources, including, but not limited to, hotfilament, radio frequency, electron cyclotron resonance, magneton andglow discharge resulting from the target bias itself. A large negativepulse with respect to the chamber is applied to the substrate 12 toaccelerate ions from the plasma toward the layer 14 of silicon dioxide16, to create a plasma sheath around the substrate 12, and to implantthe ions into the layer 14 of silicon dioxide 16. A plasma density,useful for implanting an appropriate amount of hydrogen ions into thelayer 14, ranges from about 10.sup.6 ions/cm.sup.3 to about 10.sup.11ions/cm.sup.3.

Another useful plasma source ion implantation apparatus and technique isdescribed in U.S. Pat. No. 5,354,381 to Sheng which is also incorporatedherein by reference in its entirety. The Sheng patent describes atechnique in which a “cold” cathode is used to generate the hydrogenplasma. In this process, the substrate 12 is mounted on a electrode,which is positioned in a wall of an implantation chamber. A pulsednegative voltage is applied to the electrode which creates electricfield lines with the walls of the chamber. These electric field linescause a hydrogen gas, which has been introduced into the chamber, toionize and causes positive ions from the hydrogen gas to be acceleratedtoward the substrate 12 and to become implanted into the substrate 12.

After the hydrogen ions have been implanted into the layer 14 of silicondioxide 16, the layer 18 of polycrystalline silicon 20 is formed on thelayer 14. The layer 18 of polycrystalline silicon 20 is formed on thelayer 14 by any deposition method currently in use in the art. Usefuldeposition methods include, but are not limited to, CVD, LPCVD, PECVD,MOCVD and sputtering.

By implanting hydrogen ions into the layer 14 of silicon dioxide 16 byplasma source ion implantation, the resulting layer 18 ofpolycrystalline silicon 20 is provided with a smooth morphology. By“smooth”, it is meant that, when the layer 18 is measured by atomicforce microscopy, the layer 18 of polycrystalline silicon 20 has a rootmean square (rms) deviation of from about 5 nm to about 12 nm. Themethod of the present invention provides a layer 18 of polycrystallinesilicon 20 which is smoother than either a layer of polycrystallinesilicon deposited on a non-treated layer of silicon dioxide (rms=22 nm)or a layer of polycrystalline silicon deposited on a layer of silicondioxide pretreated with an H.sub.2 gas bake (rms=33 nm). While notwishing to be bound by a particular theory, it is believed that theimplantation of the hydrogen ions in the silicon dioxide substrateincreases the number of nucleation sites for polycrystalline silicondeposition thus affecting the morphology of the subsequently depositedlayer of polycrystalline silicon.

Unlike a Kaufman ion source implantation technique, a plasma source ionimplantation apparatus does not employ a metal grid to accelerate thehydrogen ions toward the target object but instead uses the targetobject itself, in this case the substrate 12, to accelerate the ionstoward the target object. Thus, plasma source ion implantation reducesthe possibility of contamination of the target object by eliminating adevice which employs a metal grid. Further, plasma source ionimplantation can be used on smaller devices or substrates than a Kaufmanion source without increasing the likelihood for contamination of thetarget object.

The semiconductor device precursor 10 of the present invention can beused to form any semiconductor device which requires that a layer ofpolycrystalline silicon be formed over a layer of silicon dioxide.Exemplary semiconductor devices which can be formed from thesemiconductor precursor 10 include, but are not limited to, field effecttransistors, thin film transistors, dynamic random access memory devices(DRAMs), static random access memory devices (SRAMs), memory arrays andsemiconductor wafers.

FIG. 2 presents a cross sectional view of a field effect transistor 50formed by the method of the present invention. The field effecttransistor 50 is formed on a semiconductor substrate 52. The fieldeffect transistor 50 includes a gate oxide 54, a source 56 and a drain58. The gate oxide 54, the source 56 and the drain 58 are formed on thesubstrate 52. A layer 64 of polysilicon 66 is formed on the gate oxide54 to form a gate electrode 70. A pair of spacers 68 are formed on thesides of the layer 64 of polysilicon 66. A layer 72 of a field oxide 74is also formed on the substrate 52.

The substrate 52 can be formed of any material currently in use in theart to form substrates for semiconductors and integrated circuits.Desirably, the substrate 52 is formed from silicon which can be oxidizedto form the layer 72 of field oxide material 74. Other useful substrates52 include, but are not limited to, gallium arsenide, indium phosphide,polycrystalline silicon, germanium, silicon dioxide, glass and quartz.As used herein, the term “substrate” is not limited to bulk substratematerials but can also denote thinner substrates such as those used toform thin film transistors. One skilled in the art will appreciate thatsubstrate 52 can be layer or part of a larger semiconductor device.

A method for making the field effect transistor 50 is shown in FIGS.2A-2C. As an initial step, the layer 72 of the field oxide 74 is formedon the substrate 52 by means of a conventional local oxidation ofsilicon (LOCOS) process. Next, a gate oxide 54 is formed on substrate52. The surface of the substrate 52 is then conditioned or pretreated sothat the subsequently formed layer 64 of polycrystalline silicon 66 hasa smooth morphology. The surface of the substrate 52 is pretreated byimplanting hydrogen ions into the surface of the substrate 52 throughplasma source ion implantation by the method described above. FIG. 2Ashows a layer 64 of polysilicon 66 having been formed on the surface ofthe substrate 52. The layer 64 of polysilicon 66 covers and, as shown inFIG. 2A, is in contact with the gate oxide 54.

As shown in FIG. 2B, after the layer 64 of polycrystalline silicon 66has been formed on the surface of the substrate 52, the layer 64 isetched to form the gate electrode 70. The gate electrode 70 is formed byany conventional masking and etching techniques currently in use in theart.

As shown in FIG. 2C, the source 56 and the drain 58 are formed by anyconventional conductive doping technique currently in use in the art.Desirably, the source 56 and the drain 58 are formed by a self alignedtechnique. After the source 56 and the drain 58 have been formed, alayer 80 of a dielectric material 68 is formed on the gate 54 and overthe source 56 and drain 58. Typically, but not necessarily, the layer 80will be a layer of an oxidized material and is provided at a thicknesssuch that it serves as an insulating layer. Any material used in the artto form spacers would be useful for forming the layer 80 of dielectricmaterial 68. Desirably, the dielectric material 68 is silicon dioxide orsilicon nitride. The resulting field effect transistor 50 is shown inFIG. 2.

The field effect transistor 50 may also be used in a typical memoryarray, such as, for example, a static random access memory (SRAM) arrayor a dynamic random access memory (DRAM) array 100, which is shown inFIG. 3. The DRAM array 100 comprises a plurality of memory cells 102arranged in rows and columns. As shown in FIG. 3A, each of the memorycells 102 includes at least one field effect transistor 50 and onecapacitor 104. The field effect transistor 50 may be the field effecttransistor 50, described above and shown in FIG. 2. The method forforming the field effect transistor 50 is described above in connectionwith the description of FIGS. 2A to 2C. Each field effect transistor 50is coupled to a capacitor 104. The gate of the field effect transistor50 is coupled to a word line 106 via an interconnect structure. Itshould be apparent that other devices such as other transistors, bipolartransistors, resistors, other capacitors and the like, may beinterconnected with the field effect transistor 50.

The field effect transistor 50 of the present invention may also used inthe fabrication of a wafer W, as is shown in FIG. 4. The wafer Wincludes a plurality of individual die 150 formed on a semiconductorsubstrate, such as substrate 52. Wafer masks (not shown) are used toapply a desired circuit structure on each of the individual die 150. Thedesired circuit structure may comprise any of the above describedstructures, e.g., the DRAM array 100 or an SRAM array. The wafer W isprocessed using standard wafer fabrication techniques.

The semiconductor device precursor 10 and the method of the presentinvention are particularly useful in forming thin film transistors and,particularly, thin film transistors which are used to make flat paneldisplays. By providing the layer of polycrystalline silicon with asmoother morphology, a thinner layer of polycrystalline silicon isformed on the substrate. The final structure of the thin film transistorwould be thinner due to the thinner polycrystalline silicon layer and tothe layers which are subsequently deposited on the polycrystallinesilicon also being thinner.

A thin film transistor 200 is shown in cross section in FIG. 5. The thinfilm transistor 200 includes an insulating substrate 202. A layer 204 ofa semiconducting material 206 is formed on the surface of the substrate202. A source region 208 and a drain region 210 are formed on the layer204 of semiconducting material 206. A layer 212 of a dielectric material214 is formed on the layer 204 of semiconducting material 206 and coversthe source 208 and the drain 210. A layer 216 of a conducting material218 is formed on the layer 212 of dielectric material 214 to form a gateelectrode 220.

The insulating substrate 202 can be any material used to form insulatinglayers in semiconductor devices and is preferably glass, quartz orsilicon dioxide. Rather than doping a layer of silicon dioxide which issubsequently deposited on a substrate as when forming a field effecttransistor and as described above, when the thin film transistor 200 isbeing formed, the insulating substrate 202, itself, is doped withhydrogen ions by the plasma source ion implantation technique describedabove.

After the insulating substrate 202 has been doped with hydrogen ions,the layer 204 of semiconducting material 206 is formed on the substrate202 by any conventional deposition process. Useful deposition methodsinclude, but are not limited to, CVD, LPCVD, PECVD, MOCVD andsputtering. The layer 204 of semiconducting material 206 can be anymaterial used to form semiconducting layers, including, but are notlimited to, gallium arsenide, indium phosphide, polycrystalline silicon,and germanium. Desirably, the layer 204 of semiconducting material 206is formed from polycrystalline silicon. Once the layer 204 ofsemiconducting material 206 has been formed, the layer 204 is etched toisolate the various regions of semiconducting material from each otheron the surface of the substrate 202.

After the various regions of semiconducting material 204 have beenformed on the substrate 202, the source region 208 and the drain region210 are formed on the layer 204 of semiconducting material 206. Thesource region 208 and the drain region 210 can either be formed in thelayer 204 of semiconducting material 206 or formed in the layer 212 ofdielectric material 214. The source region 208 and the drain region 210are formed by any doping technique currently in use in the art. Thelayer 212 of dielectric material 214 is deposited on the layer 204 ofsemiconducting material 206. Useful deposition methods include, but arenot limited to, thermal oxidation, CVD, LPCVD, PECVD, MOCVD andsputtering. The layer 212 of dielectric material 214 can be any materialused in the semiconductor manufacturing art to form dielectric layers.Desirably, the dielectric material 214 is silicon dioxide or siliconnitride.

As a final step, a layer 216 of a conducting material 218 is formed onthe layer 212 of dielectric material 214. The layer 216 is formed in anymanner currently used in the art to form such layers. Useful depositionmethods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD andsputtering. The conducting material 218 is selected from the groupconsisting of polycrystalline silicon, metal and any conductingmaterial. The layer 216 of conducting material 218 forms the gateelectrode 220.

One skilled in the art will appreciate that the method of the presentinvention can be carried out as a stand-alone process, clustered as partof the semiconductor manufacturing process or as an in situpretreatment.

Having described the invention in detail and by reference to preferredembodiments thereof, it will be apparent that modifications andvariations are possible without departing from the scope of theinvention which is defined in the appended claims.

1-14. (canceled)
 15. A semiconductor device precursor comprising: a semiconductor substrate; silicon dioxide formed on said semiconductor substrate, the surface of said silicon dioxide having been doped with hydrogen ions deposited by a plasma source ion implantation process, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process; and polycrystalline silicon formed on said silicon dioxide, said polycrystalline silicon having a smooth morphology.
 16. The semiconductor device precursor of claim 15 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
 17. A field effect transistor comprising: a semiconductor substrate; silicon dioxide formed on at least a portion of said semiconductor substrate, the surface of said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process; polycrystalline silicon formed on at least a portion of said silicon dioxide, said polycrystalline silicon having a smooth morphology; a gate oxide formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation; and a source and a drain formed in said semiconductor substrate with a gate electrode formed on said semiconductor substrate from said polycrystalline silicon to form a field effect transistor.
 18. The transistor of claim 17 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
 19. A memory array comprising: a semiconductor substrate; silicon dioxide formed on at least a portion of said semiconductor substrate, wherein hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process; polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology; a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor; a gate oxide for each of said field effect transistors formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation; a source and a drain for each of said field effect transistors formed in said semiconductor substrate; and a gate electrode for each of said field effect transistors formed on said semiconductor substrate from said polycrystalline silicon.
 20. The memory array of claim 19 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
 21. The memory array of claim 19 comprising DRAM.
 22. The memory array of claim 19 comprising SRAM.
 23. A semiconductor wafer comprising: a wafer including a semiconductor substrate, said wafer being divided into a plurality of die; silicon dioxide formed on at least a portion of said semiconductor substrate, on each of said plurality of die hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process; polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology; a repeating series of gate oxides formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation; a repeating series of sources and drains for at least one field effect transistor formed on each of said plurality of die, said series of sources and drains being formed on said semiconductor substrate; and a repeating series of gate electrodes for at least one field effect transistor formed on each of said plurality of die, said series of gate electrodes being formed on said semiconductor substrate from said polycrystalline silicon.
 24. A thin film transistor comprising: a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass, the surface of said semiconductor substrate having hydrogen ions implanted therein by plasma source ion implantation, wherein said semiconductor substrate has reduced sputtered metal contaminants in comparison with a semiconductor substrate doped with ions deposited by a Kauffman ion implantation process; polycrystalline silicon formed on at least a portion of said semiconductor substrate, said polycrystalline silicon having a smooth morphology; insulating material formed on at least a portion of said polycrystalline silicon; a gate oxide formed from said insulating material; a source region and a drain region formed in said polycrystalline silicon; and a gate electrode formed on said insulating material. 